6.374 Analysis and Design of Digital Integrated Circuits
Device and circuit level optimization of digital building blocks. MOS device models including Deep Sub-Micron effects. Circuit design styles for logic, arithmetic, and sequential blocks. Estimation and minimization of energy consumption. Interconnect models and parasitics, device sizing and logical effort, timing issues (clock skew and jitter), and active clock distribution techniques. Memory architectures, circuits (sense amplifiers), and devices. Testing of integrated circuits. Extensive custom and standard cell layout and simulation in design projects and software labs.
6.374 will be offered this semester (Fall 2018). It is instructed by V. Sze.
This class counts for a total of 12 credits. This is a graduate-level class.
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