6.175 Constructive Computer Architecture
Illustrates a constructive (as opposed to a descriptive) approach to computer architecture. Topics include combinational and pipelined arithmetic-logic units (ALU), in-order pipelined microarchitectures, branch prediction, blocking and unblocking caches, interrupts, virtual memory support, cache coherence and multicore architectures. Labs in a modern Hardware Design Language (HDL) illustrate various aspects of microprocessor design, culminating in a term project in which students present a multicore design running on an FPGA board.
This class has 6.004 as a prerequisite.
6.175 will be offered this semester (Fall 2018). It is instructed by M. Arvind.
This class counts for a total of 12 credits.
You can find more information at the http://www.google.com/search?&q=MIT+%2B+6.175&btnG=Google+Search&inurl=https site or on the 6.175 Stellar site.
© Copyright 2015 Yasyf Mohamedali